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STA518
40V 3.5A quad power half bridge
Feature

Multipower BCD technology Minimum input output pulse width distortion 200m RdsON complementary dmos output stage CMOS compatible logic inputs Thermal protection Thermal warning output Under voltage protection Short circuit protection The device is particularly designed to make the output stage of a stereo All-Digital High Efficiency (DDXTM) amplifier capable to deliver an output power of 24W x 4 channels @ THD = 10% at Vcc 30V on 4W load in single ended configuration. It can also deliver 50 + 50W @ THD = 10% at Vcc 29V as output power on 8W load in BTL configuration and 70W @ THD = 10% at Vcc 34V on 8W in single paralleled BTL configuration. The input pins have threshold proportional to VL pin voltage. PSSO36 (slug up)
Description
STA518 is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used also as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability.
Order codes
Part number STA518 STA51813TR Temp range, C -40 to 90 -40 to 90 Package PowerSSO36 (slug up) PowerSSO36 (slug up) Packing Tube Tape & reel
May 2006
Rev 3
1/19
www.st.com 1
Contents
STA518
Contents
1 2 3 Audio application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 3.2 3.3 3.4 3.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Technical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 4.4 Logic interface and decode: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power outputs: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Parallel output / high current operation: . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Additional informations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 6 7
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
STA518
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional Pin Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VLOW, VHIGH variation with Ibias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic Truth Table (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3/19
List of figures
STA518
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Audio application circuit ( Quad single ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Low current dead time for Single End application: test circuit. . . . . . . . . . . . . . . . . . . . . . . 11 High current dead time for Bridge application: block diagram . . . . . . . . . . . . . . . . . . . . . . 11 High current dead time for Bridge application: test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . 11 STA518 Block Diagram Full-Bridge DDX(R) or Binary Modes . . . . . . . . . . . . . . . . . . . . . . . 12 STA518 Block Diagram Binary Half-Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical Stereo Full Bridge Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Typical Single BTL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power Dissipation vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power Derating Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 THD+N vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Power vs Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 THD vs Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Power vs Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 THD+N vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Dissipation vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 THD+N vs Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PSSO36 (Slug Up) Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . 17
4/19
1
STA518
Figure 1.
VCC1P 29 23 24 16 M2 14 PGND1P C41 330pF R51 6 PROTECTIONS & LOGIC 12 M5 11 10 OUTNL M4 13 R52 6 C82 100nF PGND1N R64 5K R42 20 C72 100nF OUTNL L12 22H R63 5K 28 30 21 22 33 REGULATORS 7 M17 35 9 36 M15 6 PGND2P C43 330pF OUTPR 31 20 4 M16 3 2 OUTNR M14 5 PGND2N OUTNR C52 1F VCC2N C62 100nF L14 22H 19 OUTPR R43 20 C73 100nF 8 L13 22H VCC2P 34 C42 330pF C32 820F C51 1F C61 100nF VCC1N C81 100nF R62 5K OUTPL 4 C91 1F 25 27 26 OUTPL R41 20 C71 100nF 17 L11 22H C31 820F M3 R61 5K 15 C21 2200F
+VCC
IN1A
IN1A
+3.3V
VL
CONFIG
PWRDN
PWRDN
R57 10K
R59 10K
FAULT
C58 100nF
TRI-STATE
TH_WAR
TH_WAR
IN1B
IN1B
VDD
VDD
C92 1F
4
VSS
Audio application circuit
VSS
Audio application circuit ( Quad single ended)
C58 100nF
C53 100nF
VCCSIGN
R65 5K
C33 820F
C60 100nF
VCCSIGN
C93 1F R53 6 C83 100nF R66 5K
4
IN2A
IN2A
GND-Reg
GND-Clean
IN2B 32
R67 5K
C34 820F
IN2B
GNDSUB 1
R44 20 C44 330pF
C74 100nF R54 6 C84 100nF R68 5K
C94 1F
4
D03AU1474
Audio application circuit
5/19
Pins description
STA518
2
Pins description
Figure 2. Pin Connection (top view)
VCCSign VCCSign VSS VSS IN2B IN2A IN1B IN1A TH_WAR FAULT TRI-STATE PWRDN CONFIG VL VDD VDD GND-Reg GND-Clean 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
D01AU1273
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C.
Table 1.
N 1 2;3 4 5 6 7 8;9 10 ; 11 12 13 14 15 16 ; 17 35 ; 36
Pin Function
Pin GND-SUB OUT2B Vcc2B GND2B GND2A Vcc2A OUT2A OUT1B Vcc1B GND1B GND1A Vcc1A OUT1A Vcc Sign Substrate ground Output half bridge 2B Positive supply Negative Supply Negative Supply Positive supply Output half bridge 2A Output half bridge 1B Positive supply Negative Supply Negative Supply Positive supply Output half bridge 1A Signal Positive supply Description
6/19
STA518 Table 1.
N 18 19 20 21 ; 22 23 24 25 26 27 28 29 30 31 32 33 ; 34 35 ; 36
Pins description Pin Function (continued)
Pin NC GND-clean GND-Reg Vdd VL CONFIG PWRDN TRI-STATE FAULT TH-WAR IN1A IN1B IN2A IN2B Vss Vcc Sign Not connected Logical ground Ground for regulator Vdd 5V Regulator referred to ground Logic Reference Voltage Configuration pin Stand-by pin Hi-Z pin Fault pin advisor Thermal warning advisor Input of half bridge 1A Input of half bridge 1B Input of half bridge 2A Input of half bridge 2B 5V Regulator referred to +Vcc Signal Positive supply Description
Table 2.
Functional Pin Status
Pin N. 27 27 26 26 25 25 28 28 24 24 Logical value 0 1 0 1 0 1 0 1 0 1 IC - STATUS Fault detected (Short circuit, or Thermal.) Normal Operation All powers in Hi-Z state Normal operation Low consumption Normal operation Temperature of the IC =130C Normal operation Normal Operation OUT1A=OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B)
Pin Name FAULT FAULT * TRI-STATE TRI-STATE PWRDN PWRDN THWAR THWAR
(1)
CONFIG CONFIG(2)
1. The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. 2. To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) to implemented single BTL (MONO MODE) operation for high current.
7/19
Electrical specifications
STA518
3
3.1
Electrical specifications
Absolute maximum ratings
Table 3.
Symbol VCC Vmax Top Ptot Tstg, Tj
Absolute maximum ratings
Parameter DC Supply Voltage (Pin 4,7,12,15) Maximum Voltage on pins 23 to 32 Operating Temperature Range Power Dissipation (Tcase = 70C) Storage and Junction Temperature Value 40 5.5 -40 to 90 21 -40 to 150 Unit V V C W C
3.2
Recommended operating conditions
Table 4.
Symbol VCC VL Tamb DC Supply Voltage Input Logic Reference Ambient Temperature
Recommended operating conditions (*)
Parameter Min. 10 2.7 0 3.3 Typ. Max. 36.0 5.0 70 Unit V V C
(*) performances not guaranteed beyond recommended operating conditions
3.3
Thermal data
Table 5.
Symbol Tj-case TjSD Twarn thSD
Thermal data (*)
Parameter Thermal Resistance Junction to Case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis 150 130 25 Min. Typ. Max. 1.5 Unit C/W C C C
(*) see Thermal information
3.4
Thermal information
The power dissipated within the device depends primarly on the supply voltage, load impedance and output modulation level. The PSSO36 Package of the STA518 includes an exposed thermal slug on the top of the device to provide a direct thermal path from the IC to the heatsink. For the Quad single ended application the Dissipated Power vs Ouptut Power is shown in Figure 10.
8/19
STA518
Electrical specifications Considering that for the STA518 the Thermal resistance Junction to slug is 1.5C/W and the extimated Thermal resistance due to the grease placed between slug and heat sink is 2.3C/W ( the use of thermal pads for this package is not recommended), the suitable Heat Sink Rth to be used can be drawn from the following graph Figure 11, where is shown the Derating Power vs.Tambient for different heatsinkers.
3.5
Table 6.
Electrical characteristcs
Electrical Characteristcs Refer to circuit in Figure 3 (VL = 3.3V; VCC = 30V; RL = 8; fsw = 384KHz; Tamb = 25C unless otherwise specified)
Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Power Pchannel RdsON Matching Power Nchannel RdsON Matching Low current Dead Time (static) High current Dead Time (dinamic) Turn-on delay time Turn-off delay time Rise time Resistive load; as Figure 3 Fall time Supply voltage operating voltage High level input voltage Low level input voltage Hi level Input current Low level input current Pin voltage = VL Pin voltage = 0.3V VL/2 300mV 1 1 35 0.8 1.7 3 10 25 36 VL/2 +300mV ns V V V A A A V V mA Id = 1A VCC = 35V Id = 1A Id = 1A see test circuit Figure 3 L = 22H; C = 470nF; RL = 8 Id = 3A; seeFigure 5 Resistive load; VCC = 30V Resistive load; VCC = 30V 95 95 10 20 50 100 100 25 Test conditions Min. Typ. 200 Max. 270 50 Unit m A % % ns ns ns ns ns
Symbol RdsON Idss gN gP Dt_s Dt_d td ON td OFF tr tf VCC VIN-H VIN-L IIN-H IIN-L IPWRDNH
Hi level PWRDN pin input current VL = 3.3V Low logical state voltage VLow (pin PWRDN, TRISTATE) (1) High logical state voltage VHigh (pin PWRDN, TRISTATE) (1) VL = 3.3V VL = 3.3V
VLOW VHIGH IVCCPWRDN
Supply current from Vcc in Power PWRDN = 0 Down
9/19
Electrical specifications Table 6. Electrical Characteristcs (continued) Refer to circuit in Figure 3 (VL = 3.3V; VCC = 30V; RL = 8; fsw = 384KHz; Tamb = 25C unless otherwise specified)
Parameter Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Supply current from Vcc in Tristate Supply current from VCC in operation (both channel switching) Isc (short circuit current limit) (2) Undervoltage protection threshold Output minimum pulse width No Load 70 Test conditions Min. Typ. Max.
STA518
Symbol
Unit
IFAULT
Vpin = 3.3V
1
mA
IVCC-hiz
VCC = 30V; Tri-state = 0 VCC = 30V; Input pulse width = 50% Duty; Switching Frequency = 384kHz; No LC filters; VCC = 30V 3.5
22
mA
IVCC
50
mA
IVCC-q VUV tpw_min
6 7 150
A V ns
1. The Table 7 explains the VLOW, VHIGH variation with Ibias. 2. See relevant Application Note AN1994
Table 7.
VLOW, VHIGH variation with Ibias
VL 2.7 3.3 5 VLow min 0.7 0.8 0.85 VHigh max 1.5 1.7 1.85 Unit V V V
Table 8.
TRI-STATE 0 1 1 1 1
Logic Truth Table (see Figure 4)
INxA x 0 0 1 1 INxB x 0 1 0 1 Q1 OFF OFF OFF ON ON Q2 OFF OFF ON OFF ON Q3 OFF ON ON OFF OFF Q4 OFF ON OFF ON OFF OUTPUT MODE Hi-Z DUMP NEGATIVE POSITIVE Not used
10/19
STA518 Figure 3.
Electrical specifications Low current dead time for Single End application: test circuit.
OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTxY
M57
DTf
INxY
R 8
+ -
V67 = vdc = Vcc/2
D03AU1458
gnd
Figure 4.
High current dead time for Bridge application: block diagram
+VCC
Q1 INxA OUTxA
Q2 OUTxB INxB
Q3
Q4
GND
D00AU1134
Figure 5.
High current dead time for Bridge application: test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC
Duty cycle=A
DTout(A) M58 Q1 OUTA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTB M64
Duty cycle=B
DTin(A) INA
DTin(B) INB
Iout=4A M57 Q3
Iout=4A Q4 M63
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
D03AU1517
11/19
Technical information
STA518
4
Technical information
The STA518 is a dual channel H-Bridge that is able to deliver 50W per channel (@ THD=10% RL = 8, VCC = 29V) of audio output power in high efficiency. The STA518 converts both DDX and binary-controlled PWM signals into audio power at the load. It includes a logic interface , integrated bridge drivers, high efficiency MOSFET outputs and thermal and short circuit protection circuitry. In DDX mode, two logic level signals per channel are used to control high-speed MOSFET switches to connect the speaker load to the input supply or to ground in a Bridge configuration, according to the damped ternary Modulation operation. In Binary Mode operation , both Full Bridge and Half Bridge Modes are supported. The STA518 includes over-current and thermal protection as well as an under-voltage Lockout with automatic recovery. A thermal warning status is also provided. Figure 6. STA518 Block Diagram Full-Bridge DDX(R) or Binary Modes
INL[1:2] INR[1:2] VL PWRDN TRI-STATE OUTPL
Logic I/F and Decode
Left H-Bridge
OUTNL
FAULT TWARN
Protection Circuitry Regulators
OUTPR
Right H-Bridge
OUTNR
Figure 7.
STA518 Block Diagram Binary Half-Bridge Mode
INL[1:2] INR[1:2] VL PWRDN TRI-STATE
Logic I/F and Decode
LeftA -Bridge LeftB -Bridge RightA -Bridge RightB -Bridge
OUTPL
OUTNL
FAULT TWARN
Protection Circuitry Regulators
OUTPR
OUTNR
4.1
Logic interface and decode:
The STA518 power outputs are controlled using one or two logic level timing signals. In order to provide a proper logic interface, the Vbias input must operate at the dame voltage as the DDX control logic supply. Protection circuitry:
12/19
STA518
Technical information The STA518 includes protection circuitry for over-current and thermal overload conditions. A thermal warning pin (pin.28) is activated low (open drain MOSFET) when the IC temperature exceeds 130C, in advance of the thermal shutdown protection. When a fault condition is detected , an internal fault signal acts to immediately disable the output power MOSFETs, placing both H-Bridges in high impedance state. At the same time an open-drain MOSFET connected to the fault pin (pin.27) is switched on. There are two possible modes subsequent to activating a fault: 1. SHUTDOWN mode: with FAULT (pull-up resistor) and TRI-STATE pins independent, an activated fault will disable the device, signaling low at the FAULT output. The device may subsequently be reset to normal operation by toggling the TRI-STATE pin from High to Low to High using an external logic signal. AUTOMATIC recovery mode: This is shown in the Audio Application Circuit of Quad single Ended). The FAULT and TRI-STATE pins are shorted together and connected to a time constant circuit comprising R59 and C58. An activated FAULT will force a reset on the TRI-STATE pin causing normal operation to resume following a delay determined by the time constant of the circuit. If the fault condition is still present , the circuit operation will continue repeating until the fault condition is removed . An increase in the time constant of the circuit will produce a longer recovery interval. Care must be taken in the overall system design as not to exceed the protection thesholds under normal operation.
2.
4.2
Power outputs:
The STA518 power and output pins are duplicated to provide a low impedance path for the device's bridged outputs. All duplicate power, ground and output pins must be connected for proper operation. The PWRDN or TRI-STATE pins should be used to set all MOSFETS to the Hi-Z state during power-up until the logic power supply, VL , is settled.
4.3
Parallel output / high current operation:
When using DDX Mode output , the STA518 outputs can be connected in parallel in order to increase the output current capability to a load. In this configuration the STA518 can provide 70W into 8 ohm. This mode of operation is enabled with the CONFIG pin (pin.24) connected to VREG1 and the inputs combined INLA=INLB, INRA=INRB and the outputs combined OUTLA=OTLB, OUTRA=OUTRB.
4.4
Additional informations:
Output Filter: A passive 2nd-order passive filter is used on the STA518 power outputs to reconstruct an analog Audio Signal . System performance can be significantly affected by the output filter design and choice of passive components. A filter design for 6ohm/8ohm loads is shown in the Typical Application circuit of Figure 9. Quad Single ended circuit (Figure 1) shows a filter for 1/2 bridge mode, 4 ohm loads.
13/19
Technical information Figure 8.
STA518 Typical Stereo Full Bridge Configuration to Obtain 50+50W @ THD = 10%, RL = 8, VCC =29V
VCC1A IN1A IN1A VL CONFIG PWRDN PWRDN FAULT 29 23 24 25 27 26 TRI-STATE PROTECTIONS & LOGIC M5 28 30 21 22 33 34 M17 VCCSIGN VCCSIGN IN2A IN2A GND-Reg GND-Clean 35 8 9 36 31 20 19 M16 M15 REGULATORS 7 VCC2A C32 1F OUT2A OUT2A 6 GND2A M4 13 M2 M3 15 17 16 C30 1F OUT1A OUT1A 14 GND1A C52 330pF +VCC C55 1000F
L18 22H C20 100nF R98 6 C99 100nF C23 470nF C101 100nF
+3.3V
R57 10K
R59 10K C58 100nF
12
VCC1B C31 1F OUT1B OUT1B GND1B R63 20 R100 6 C21 100nF L19 22H
8
11 10
TH_WAR IN1B
TH_WAR IN1B VDD VDD VSS VSS
C58 100nF
C53 100nF C60 100nF
L113 22H C110 100nF C109 330pF R103 6 R104 20
4
VCC2B C33 1F OUT2B OUT2B
R102 6 C111 100nF
3 2
C107 100nF C108 470nF C106 100nF
8
IN2B
IN2B GNDSUB
32 M14
L112 22H
1
5
GND2B
D00AU1148B
Figure 9.
Typical Single BTL Configuration to Obtain 70W @ THD 10%, RL = 8, VCC = 34V (note 1))
VL 100nF GND-Clean GND-Reg 23 18 17 16 11 10 N.C. 22H 19 20 OUT1A OUT1A OUT1B OUT1B OUT2A 9 8 OUT2B 3 2 VCC1A 1F X7R 2200F 63V OUT2B 22H 32V OUT2A 330pF 22 1/2W 6.2 1/2W 6.2 1/2W 100nF FILM 100nF X7R 470nF FILM 100nF X7R 100nF FILM
+3.3V
10K
100nF X7R
VDD VDD CONFIG
21 22 24 28 25 27 26
8
TH_WAR nPWRDN 10K
TH_WAR PWRDN FAULT TRI-STATE 100nF IN1A IN1B IN2A IN2B VSS VSS 100nF X7R 100nF X7R Add. VCCSIGN VCCSIGN GNDSUB
15
29 30 31 32 33 34
12
VCC1B VCC2A
IN1A
7
32V 1F X7R
IN1B
4 14
VCC2B GND1A GND1B
35
13 GND2A
36 1
6 GND2B 5
D04AU1549
Note:
1
"A PWM modulator as driver is needed . In particular, this result is performed using the STA308+STA518+STA50X demo board". Peak Power for t 1sec
14/19
STA518
Characterization curves
5
Characterization curves
The following characterization are obtained using the quad single ended configuration (Figure 1) with STA308A controller Figure 10. Power Dissipation vs Output Power Figure 11. Power Derating Curve
Pd (W)16
14 12 10 8 6 4 2 0 0 4 8 12 16 20 24
Pd(W)
25
1
Vcc=30V Rl=4ohm F =1Kz
1)Infinite 2) 1.5 C/W
20 15 10 5
5 4
3
2
3) 3 C/W 4) 4.5 C/W 5) 6 C/W
0
20
40
60
80
100 120 140 160
4 x Pout (W)
Tambient(C)
Figure 12. THD+N vs Output Power
THD(%) 10 5 Vcc = 26V Rl = 4 ohm 2 1 F = 1KHz Single Ended
Figure 13. Output Power vs Supply Voltage
Pout(W) 30 27.5 25 22.5 20 17.5 15 THD=10% Rl=4 ohm F=1KHz Single Ended
0.5
12.5 10 THD=1%
0.2 0.1 100m
7.5 5
200m
500m
1
2 Pout(W)
5
10
20 30
2.5
+10
+12
+14
+16
+18
+20 Vdc
+22
+24
+26
+28
+30
Figure 14. THD vs Frequency
THD(%) 1 0.5
0.2 Rl=4 ohm Pout=1W 0.05 Single Ended
0.1
0.02
0.01 20
50
100
200
500 1k Freq(Hz)
2k
5k
10k
20k
15/19
Characterization curves
STA518
The following characterizations are obtained using the stereo full bridge configuration (Figure 8) with STA308A controller. Figure 15. Output Power vs Supply Voltage
o(W) 90 80 70 60
THD=10%
Figure 16. THD+N vs Output Power
THD(%) 10 5
Rl=8ohm F=1KHz
2 1 0.5 0.2 0.1
THD=1% Single Parallel BTL
Vcc=29V Rl=8ohm F=1KHz Double BTL
50
Stereo Full BTL
40 30 20 10 0 +10
0.05 0.02 0.01 100m 200m 500m 1 2 Pout(W) 5 10 20 60
+12
+14
+16
+18
+20
+22
+24
+26
+28
+30
+32
+34 +36
Vsupply(V)
Figure 17. Power Dissipation vs Output Power
Pd (W) 12
10 8 6 4 2 0 0 10 20 30 2 X Pout (W) 40 50
Vcc=29V Rl=8ohm F=1KHz
The following characterizations are obtained using the single BTL configuration (Figure 9) with STA308A controller. Figure 18. THD+N vs Output Power
THD(%) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 100m Vcc=34V Rl=8ohm F=1KHz Single BTL
200m
500m
1
2
5 Pout(W)
10
20
50 80
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STA518
Package information
6
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 19. PSSO36 (Slug Up) Mechanical Data & Package Dimensions
DIM. A A2 a1 b c D (1) E (1) e e3 F G G1 H h L M N O Q S T U X Y MIN. 2.15 2.15 0 0.18 0.23 10.10 7.4 0.50 8.50 2.3 0.10 0.06 10.50 0.40 0.85 4.3 10 (max) 1.2 0.8 2.9 3.65 1.0 4.10 6.50 4.70 7.10 0.161 0.256 0.047 0.031 0.114 0.144 0.039 0.185 0.279 mm TYP. MAX. 2.47 2.40 0.075 0.36 0.32 10.50 7.6 MIN. 0.084 0.084 0 0.007 0.009 0.398 0.291 0.020 0.035 0.090 0.004 0.002 0.413 0.016 0.033 0.169 inch TYP. MAX. 0.097 0.094 0.003 0.014 0.012 0.413 0.299
OUTLINE AND MECHANICAL DATA
10.10 0.55
0.398 0.022
(1) "D and E" do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006") (2) No intrusion allowed inwards the leads. (3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side
PowerSSO-36 (slug-up)
7618147 A
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Revision history
STA518
7
Revision history
Table 9.
Date 19-Aug-2004 11-Nov-2004 18-May-2006
Document revision history
Revision 1 2 3 Initial release. Changed symbol in "Electrical Characteristics". Changed operating temperature range value to -40 to 90C (seeTable 3). Changes
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STA518
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